1. Field of the Invention
The present invention relates to an information processing device comprising a plurality of processing units and a data control method in the information processing device.
2. Description of the Related Art
Information processing devices such as servers have been widely used in recent years in a variety of fields. Web servers processing millions of accesses per day and transaction servers used in financial institutions or communication companies are the typical servers.
Because such information processing devices are required to have a high processing capability, they most often have a multiprocessor configuration carrying a plurality of processing units (CPU (Central Processing Unit), MPU (Micro Processing Unit) etc.) in one information processing device. In the information processing devices with a multiprocessor configuration, control has to be conducted to maintain consistency (memory consistency, cache coherency) of data stored in a main memory and a cache provided in each processing unit so that each processing unit can independently access the main memory.
In the information processing devices with a multiprocessor configuration, the consistency is most often controlled with a system controller conducting intermediate processing of the main memory and each processing unit. Further, as a control for maintaining the consistency, for example, in the case where a read request relating to the same request is generated, while the system controller stores data (write data) that will be written into the main memory, the system controller waits till writing of the write data into the main memory is completed and then processes the read request.
As a result, the execution time required for processing the read requests is increased and the processing capability of the information processing device is degraded. Accordingly, a technology for improving the processing capability of read requests in an information processing device by using a store buffer for storing temporarily the data immediately prior to writing to the main memory or cache memory has been suggested as prior art technology (Japanese Patent Application Laid-open No. H6-301600 and H3-288245).
However, data stored in the store buffer is stored as a result of arbitration relating to read requests and write requests from each processing unit that are stored in a read cue or write cue provided in the previous stage. Therefore, the problem is that it is necessary to wait for arbitration in order to use the store buffer (and data stored therein).